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 Advanced Power MOSFET
FEATURES
Avalanche Rugged Technology Rugged Gate Oxide Technology Lower Input Capacitance Improved Gate Charge Extended Safe Operating Area Lower Leakage Current : 10 A (Max.) @ VDS = -200V Low RDS(ON) : 0.581 (Typ.)
1 2 3
SFS9630
BVDSS = -200 V RDS(on) = 0.8 ID = -4.4 A
TO-220F
1.Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol VDSS ID IDM VGS EAS IAR EAR dv/dt PD TJ , TSTG TL Characteristic Drain-to-Source Voltage Continuous Drain Current (TC=25 C) Continuous Drain Current (TC=100 C) Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (TC=25 C) Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8 " from case for 5-seconds
o o o
Value -200 -4.4 -3.3
1 O
Units V A A V mJ A mJ V/ns W W/ C
o
-18 + 30 _ 258 -4.4 3.3 -5.0 33 0.26 - 55 to +150
O 1 O 1 O 3 O
2
o
C
300
Thermal Resistance
Symbol RJC RJA Characteristic Junction-to-Case Junction-to-Ambient Typ. --Max. 3.79 62.5 Units
o
C/W
Rev. B
(c)1999 Fairchild Semiconductor Corporation
SFS9630
Symbol BVDSS BV/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Characteristic Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse Drain-to-Source Leakage Current Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain( " Miller " ) Charge Min. Typ. Max. Units -200 --2.0 ------------------0.17 ------3.7 740 125 49 14 22 41 17 29 5.8 13.6 ---4.0 -100 100 -10 -100 0.8 -965 185 75 35 55 90 45 36 --nC ns pF A V V nA
P-CHANNEL POWER MOSFET
Electrical Characteristics (TC=25oC unless otherwise specified)
Test Condition VGS=0V,ID=-250A See Fig 7 VDS=-5V,ID=-250A VGS=-30V VGS=30V VDS=-200V VDS=-160V,TC=125 C VGS=-10V,ID=-2.2A VDS=-40V,ID=-2.2A
4 O 4 O
o
o V/ C ID=-250A
VGS=0V,VDS=-25V,f =1MHz See Fig 5 VDD=-100V,ID=-6.5A, RG=12 See Fig 13
45 OO
VDS=-160V,VGS=-10V, ID=-6.5A See Fig 6 & Fig 12
45 OO
Source-Drain Diode Ratings and Characteristics
Symbol IS ISM VSD trr Qrr Characteristic Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
1 O
Min. Typ. Max. Units --------160 0.96 -4.4 -18 -5.0 --A V ns C
Test Condition Integral reverse pn-diode in the MOSFET TJ=25 C,IS=-4.4A,VGS=0V TJ=25 C,IF=-6.5A diF/dt=100A/s
4 O
o o
O
4
Notes ; 1 O Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature 2 O L=20mH, I =-4.4A, V =-50V, R =27*, Starting T =25 C _ 3 _ < O I <-6.5A, di/dt <400A/s, V _ BV , Starting T =25 C 4 Pulse Test : Pulse Width = 250 s, Duty Cycle _ 2% < O 5 O Essentially Independent of Operating Temperature
o AS DD G J o SD DD DSS J
P-CHANNEL POWER MOSFET
Fig 1. Output Characteristics
V GS
SFS9630
Fig 2. Transfer Characteristics
[A] -ID , Drain Current
[A]
Top :
10
1
-ID , Drain Current
- 15 V - 10 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom : - 4.5 V
101
100
100
150 oC 25 oC @ Notes : 1. V = 0 V GS 2. V = -40 V DS - 55 oC 3. 250 s Pulse Test
@ Notes : 1. 250 s Pulse Test 2. T = 25 oC C 10-1 10-1
0 10
101
10-1
2
4
6
8
10
-VDS , Drain-Source Voltage [V]
-VGS , Gate-Source Voltage [V]
RDS(on) , [ ] Drain-Source On-Resistance
Fig 3. On-Resistance vs. Drain Current
2.5
[A]
Fig 4. Source-Drain Diode Forward Voltage
-IDR , Reverse Drain Current
2.0
101
1.5 V = -10 V GS 1.0
100 150 oC 25 oC @ Notes : 1. V = 0 V GS 2. 250 s Pulse Test
0.5 VGS = -20 V 0.0 0 4 8 12 16 20 24 @ Note : T = 25 oC J
10-1 0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage
C = C + C ( Cds= shorted ) iss gs gd C =C +C oss ds gd
Fig 6. Gate Charge vs. Gate-Source Voltage
[V]
1500
[pF]
C iss 1000
C =C rss gd
-VGS , Gate-Source Voltage
10
VDS = -40 V VDS = -100 V VDS = -160 V
Capacitance
C oss @ Notes : 1. V = 0 V GS 2. f = 1 MHz
5
500
C rss
@ Notes : I =-6.5 A D 0 0 5 10 15 20 25 30
0 0 10
1 10
-VDS , Drain-Source Voltage [V]
QG , Total Gate Charge [nC]
SFS9630
Drain-Source Breakdown Voltage
P-CHANNEL POWER MOSFET
Fig 8. On-Resistance vs. Temperature
Drain-Source On-Resistance
3.0
Fig 7. Breakdown Voltage vs. Temperature
1.2
-BV , (Normalized) DSS
RDS(on) , (Normalized)
2.5
1.1
2.0
1.0
1.5
1.0 @ Notes : 1. V = -10 V GS 2. I = -3.3 A D -50 -25 0 25 50 75 100 125 150 175
0.9
@ Notes : 1. V = 0 V GS 2. I = -250 A D -50 -25 0 25 50 75 100
o
0.5
0.8 -75
125
150
175
0.0 -75
TJ , Junction Temperature [ C]
TJ , Junction Temperature [oC]
Fig 9. Max. Safe Operating Area
[A]
102 Operation in This Area is Limited by R DS(on)
Fig 10. Max. Drain Current vs. Case Temperature
6
-ID , Drain Current
[A]
5
101
-ID , Drain Current
0.1 ms 1 ms 10 ms
4
3
100
DC @ Notes : 1. T = 25 oC C 2. T = 150 oC J 3. Single Pulse
2
1
10-1 100 101 102 0 25 50 75 100 125 150
-VDS , Drain-Source Voltage [V]
Tc , Case Temperature [oC]
Fig 11. Thermal Response
Thermal Response
D=0.5 10 0 0.2 0.1 0.05 0.02 10- 1 0.01 single pulse @ Notes : 1. Z J C (t)=3.79
o C/W Max. 2. Duty Factor, D=t1 /t 2
3. TJ M -T C =P D M *Z J C (t)
P. DM t1. t2.
Z
JC
(t) ,
10- 5
10- 4
10 - 3
10 - 2
10 - 1
100
10 1
t 1 , Square Wave Pulse Duration
[sec]
P-CHANNEL POWER MOSFET
Fig 12. Gate Charge Test Circuit & Waveform
SFS9630
" Current Regulator "
50K 12V 200nF 300nF
Same Type as DUT
VGS Qg
-10V
VDS VGS DUT
-3mA
Qgs
Qgd
R1
Current Sampling (IG) Resistor
R2
Current Sampling (ID) Resistor
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
RL Vout Vin RG DUT -10V Vout
90%
t on
t off tr td(off) tf
VDD
( 0.5 rated VDS )
td(on)
Vin
10%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
LL VDS
Vary tp to obtain required peak ID
BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD
tp
ID VDD
Time VDS (t)
RG DUT -10V
tp
C
VDD
ID (t) IAS BVDSS
SFS9630
P-CHANNEL POWER MOSFET
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
+ VDS DUT -IS L Driver RG VGS
Compliment of DUT (N-Channel)
VGS
VDD
* dv/dt controlled by "RG" * IS controlled by Duty Factor "D"
VGS ( Driver )
Gate Pulse Width D = -------------------------Gate Pulse Period
10V
Body Diode Reverse Current
IS ( DUT )
IRM
di/dt IFM , Body Diode Forward Current
Vf VDS ( DUT )
Body Diode Forward Voltage Drop Body Diode Recovery dv/dt
VDD
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrenchTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 TinyLogicTM
UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.


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